1. Field of the Invention
The present invention relates to a solid-state imaging device that performs analog-to-digital (hereinafter referred to as “AD”) conversion to convert an analog voltage signal output from a pixel into binary digital data.
Priority is claimed on Japanese Patent Application No. 2011-231865, filed Oct. 21, 2011, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, imaging devices, such as digital still cameras or digital video cameras, that can acquire images captured using solid-state imaging devices (hereinafter referred to as “image sensors”) as digital data and store or edit the digital data have been widely spread. As image sensors used in such imaging devices, charge coupled device (CCD)-type image sensors have most generally been widely used. However, in recent years, since there are demands for further miniaturization and further low power consumption of the image sensors, complementary metal oxide semiconductor (CMOS) type image sensors have been popularized and spread. With miniaturization and low power consumption of imaging devices, miniaturization and low power consumption of AD conversion circuits used in image sensors have been achieved, and an AD conversion circuit has been suggested (for example, see Japanese Patent No. 3064644).
FIG. 15 is a diagram illustrating the configuration of an AD conversion circuit according to the related art. The AD conversion circuit shown in FIG. 15 includes a pulse phase difference encoding circuit 2 that encodes a phase difference between pulse signals PA and PB and a control circuit 4 that generates the pulse signals PA and PB. The pulse phase difference encoding circuit 2 includes a pulse circling circuit 10 (delay circuit), a counter 12, a latch circuit 14, a pulse selector 16, an encoder 18, and a signal processing circuit 19.
The pulse circling circuit 10 has a configuration in which inverting circuits (delay elements: one negative AND circuit NAND and a plurality of (even) inverters INV) receiving a pulse signal PA from one input end to operate are connected in a ring (circular) shape and an analog signal Vin, which is an input signal, is applied as a supply voltage of each inverting circuit. The counter 12 counts the number of times the pulse signal is circled within the pulse circling circuit 10 based on transition of the logic state of a signal output from the last inverter INV (the inverter INV installed at the previous stage of the negative AND circuit NAND) of the last stage of the pulse circling circuit 10 and generates binary digital data.
The latch circuit 14 latches the digital data output from the counter 12. The pulse selector 16 acquires the signal output from each converting circuit of the pulse circling circuit 10 and outputs a signal indicating the position of the pulse signal circling within the pulse circling circuit 10 based on the logic state of the signal output from each converting circuit. The encoder 18 encodes the signal output from the pulse selector 16 to generate digital data based on the circling position of the pulse signal.
The signal processing circuit 19 generates binary digital data DO1 indicating the phase difference between the pulse signals PA and PB by setting the digital data output from the latch circuit 14 and the digital data output from the encoder 18 to high-order bits and low-order bits, respectively, and reducing the data of the high-order bits from the data of the low-order bits. The digital data DO1 generated by the signal processing circuit 19 is output to the outside via a data output line 20.
The AD conversion circuit counts the number of times the pulse signal is circled in the pulse circling circuit 10 within a period (hereinafter referred to as a “sampling period”) in which the AD conversion is performed based on the fact that a delay time given to the pulse signal by each inverting circuit is changed by the supply voltage. Further, the AD conversion circuit uses the counted count value and the value obtained by encoding the logic state of the signal output from each inverting circuit in the pulse circling circuit 10 as high-order bits and low-order bits, respectively, to synthesize the output values of the high-order bits and the low-order bits. Since the delay time given to the pulse signal by each inverting circuit is changed by the supply voltage, the number of inverting circuits through which the pulse signal passes within a predetermined period is the number corresponding to the level of a pixel signal, and thus the digital data corresponding to this number is generated.
A CMOS type image sensor (CMOS type image sensor of a column ADC system) in which the AD conversion circuit is provided in each column and a signal output from each pixel is subjected to AD conversion has been suggested (for example, see Japanese Unexamined Patent Application, First Publication No. 2010-283580). In the CMOS type image sensor of the column ADC system, a variation in the gain or offset component between the AD conversion circuits in the columns is corrected. Accordingly, a variation in the gain or offset component between the columns generally needs to be corrected based on the AD conversion result of a signal serving as a reference.
In the CMOS type image sensor of the column ADC system including the above-described AD conversion circuits, however, interference of electromagnetic noise between the adjacent columns or phase noise of the pulse circling circuit itself occurs, since the pulse circling circuits which are oscillation circuits are installed to be adjacent to each other at an interval of a pixel pitch. Since the output state of the inverting circuit is changed between H (High) and L (Low) due to the circling of the pulse in the pulse circling circuit, the supply voltage or a GND voltage of the inverting circuit fluctuates, the delay time of the pulse in the inverting circuit fluctuates due to the fluctuation thereof, and noise is superimposed on the AD conversion result. This noise is the phase noise of the pulse circling circuit itself. A vertical stripe may occur for a column in which the offset component may not be corrected on an image and the variation in the offset component between the columns may not be corrected due to the fact that such noise is superimposed as low-frequency noise on the AD conversion result.
Japanese Patent No. 03292182 discloses a method of removing a low-frequency noise superimposed on the AD conversion circuit. In Japanese Patent No. 03292182, the low-frequency noise is removed by calculating a ratio between the AD conversion result of an analog signal and the AD conversion result of a reference voltage used to remove the low-frequency noise.